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february 2012 ? 2011 fairchild semiconductor corporation www.fairchildsemi.com FL7730MY ? rev. 1.0.3 FL7730MY ? single-stage primary-si de-regulation pwm controller fo r pfc and led dimmable driving FL7730MY single-stage primary-side-regulation pwm controller for pfc and led dimmable driving features ? compatible with traditional triac control (no need to change existing lamp infrastructure: wall switch & wire) ? compatible with non-dimming lamp designs ? cost-effective solution without input bulk capacitor and feedback circuitry ? power factor correction (pfc) ? accurate constant-current (cc) control, independent online volta ge, output voltage, magnetizing inductance variation ? line voltage compensation for cc control ? linear frequency control for better efficiency and simple design ? open-led protection ? short-led protection ? cycle-by-cycle current limiting ? over-temperature protection with auto restart ? low startup current: 20 a ? low operating current: 5ma ? frequency hopping for better emi performance ? sop-8 package available ? application voltage range: 80v ac ~ 308v ac applications ? led lighting system description this highly integrated pwm controller, FL7730MY, provides several features to enhance the performance of single-stage flyback converters. the proprietary topology, truecurrent?, enables the simplified circuit design for led lighting applications. triac dimming is smoothly managed by dimming brightness control without flicker. by using single-stage topology with primary-side regulation, an led lighting board can be implemented with few external components and minimized cost. it does not require an input bulk capacitor or feedback circuitry. to implement good power factor and low total harmonic distortion, constant on-time control is utilized with an external capacitor connected to the comi pin. precise constant-current control regulates accurate output current versus changes in input voltage and output voltage. the operating frequency is proportionally changed by the output voltage to guarantee discontinuous conduction mode (dcm) operation with higher efficiency and simpler design. the FL7730MY provides protections such as open-led, short-led, and over-temperature protections. current-limit level is automatically reduced to minimize output current and protect external components in a short-led condition. the FL7730MY frequency-hopping function in the oscillator improves em i performance. the FL7730MY controller is available in an 8-pin sop package. ordering information part number operating temperature range package packing method FL7730MY -40c to +125c 8-lead, small outline package (sop-8) tape & reel
? 2011 fairchild semiconductor corporation www.fairchildsemi.com FL7730MY ? rev. 1.0.3 2 FL7730MY ? single-stage primary-si de-regulation pwm controller fo r pfc and led dimmable driving application diagram trans bridge diode triac dimmer comi dim gnd cs gnd vdd vs fl7730 gate 1 3 6 5 8 7 2 4 fuse line input figure 1. typical application internal block diagram s r q 4 internal bias 7 vdd comi osc bcm truecurrent? calculation leb gate driver 2 gate 1cs v ref 6 vs 3 gnd 5 dim + - - + - + - + triac dimming function 8 gnd sawtooth generator v ocp s r q - + v ovp v dd good v dd good tsd shutdown line compensator linear frequency controller v s freq. error amp. t dis detector ocp level controller vs dcm sample & hold figure 2. functional block diagram
? 2011 fairchild semiconductor corporation www.fairchildsemi.com FL7730MY ? rev. 1.0.3 3 FL7730MY ? single-stage primary-si de-regulation pwm controller fo r pfc and led dimmable driving marking information zxytt tpm 7730 figure 3. top mark pin configuration figure 4. pin configuration pin definitions pin # name description 1 cs current sense . this pin connects a current-sense resist or to detect the mosfet current for the output-current regulation in constant current regulation. 2 gate pwm signal output . this pin uses the internal totem-p ole output driver to drive the power mosfet. 3 gnd ground 4 vdd power supply . ic operating current and mosfet driving current are supplied using this pin. 5 dim dimming . this pin controls the dimming operation of led lighting. 6 vs voltage sense . this pin detects the output voltage info rmation and discharge time for linear frequency control and constant-current regulation. this pin connects divider resistors from the auxiliary winding. 7 comi constant current loop compensation . this pin is the output of the transconductance error amplifier. 8 gnd ground f : fairchild logo z: plant code x: 1-digit year code y: 1-digit week code tt: 2-digit die run code t: package type (m=sop) p: z: pb free, y: green package m: manufacture flow code
? 2011 fairchild semiconductor corporation www.fairchildsemi.com FL7730MY ? rev. 1.0.3 4 FL7730MY ? single-stage primary-si de-regulation pwm controller fo r pfc and led dimmable driving absolute maximum ratings stresses exceeding the absolute maximum ratings may damage the device. the device may not function or be operable above the recommended operating conditions and stressi ng the parts to these levels is not recommended. in addition, extended exposure to stresses above the recomm ended operating conditions may affect device reliability. the absolute maximum ratings are stress ratings only. symbol parameter min. max. unit v vdd dc supply voltage (1,22) 30 v v vs vs pin input voltage -0.3 7.0 v v cs cs pin input voltage -0.3 7.0 v v dim dim pin input voltage -0.3 7.0 v v comi comi pin input voltage -0.3 7.0 v v gate gate pin input voltage -0.3 30.0 v p d power dissipation (t a 50c) 633 mw ja thermal resistance (junction to air) 158 c /w jc thermal resistance (junction to case) 39 c /w t j maximum junction temperature 150 c t stg storage temperature range -55 150 c t l lead temperature (soldering, 10 seconds) 260 c esd electrostatic discharge capability human body model, jesd22-a114 6 kv charged device model, jesd22-c101 2 notes: 1. stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. 2. all voltage values, except differential voltag es, are given with respect to the gnd pin. recommended operating conditions the recommended operating conditions table defines the conditions for actual device operation. recommended operating conditions are specified to ensur e optimal performance to the datasheet specificati ons. fairchild does not recommend exceeding them or designing to absolute maximum ratings. symbol parameter min. max. unit t a operating ambient te mperature -40 125 c
? 2011 fairchild semiconductor corporation www.fairchildsemi.com FL7730MY ? rev. 1.0.3 5 FL7730MY ? single-stage primary-si de-regulation pwm controller fo r pfc and led dimmable driving electrical characteristics v dd =20v and t a =25c unless otherwise specified. symbol parameter conditions min. typ. max. units vdd section v dd-on turn-on threshold voltage 14.5 16.0 17.5 v v dd-off turn-off threshold voltag e 6.75 7.75 8.75 v i dd-op operating current maximum frequency, c load = 1nf 3 4 5 ma i dd-st startup current v dd = v dd-on ? 0.16v 2 20 a v ovp v dd over-voltage-protection 22.0 23.5 25.0 v gate section v ol output voltage low v dd =20v,i gate =-1ma 1.5 v v oh output voltage high v dd =10v,i gate =+1ma 5 v i source peak sourcing current v dd = 10 ~ 20v 60 ma i sink peak sinking current v dd = 10 ~ 20v 180 ma t r rising time c load = 1nf 100 150 200 ns t f falling time c load = 1nf 20 60 100 ns v clamp output clamp voltage 12 15 18 v oscillator section f max-cc maximum frequency in cc 60 65 70 khz f min-cc minimum frequency in cc 21.0 23.5 26.0 khz vs max-cc v s for maximum frequency in cc f = f max -2khz 2.25 2.35 2.45 v vs min-cc v s for minimum frequency in cc f = f min +2khz 0.55 0.85 1.15 v f hopping frequency hopping range 1.8 2.9 4.0 khz f hopping frequency hopping period 2 ms t on(max) maximum turn-on time 12 14 16 ? s current sense section v rv reference voltage 2.475 2.500 2.525 v v ccr eai voltage for constant current regulation v cs = 0.44v 2.38 2.43 2.48 v t leb leading-edge blanking time 300 ns t min minimum on time in cc v comi = 0v 600 ns t pd propagation delay to gate 50 100 150 ns t tdis-bnk t dis blanking time of vs 1.5 ? s i comi-bnk vs current for comi blanking 100 ? a current-error amplifier section ? gm transconductance 85 ? mho ? i comi-sink comi sink current v eai =3v, v comi =5v 28 38 ? a i comi-source comi source current v eai =2v, v comi =0v 28 38 ? a v comi-hgh comi high voltage v eai =2v 4.9 v v comi-low comi low voltage v eai =3v 0.1 v ? continued on the following page?
? 2011 fairchild semiconductor corporation www.fairchildsemi.com FL7730MY ? rev. 1.0.3 6 FL7730MY ? single-stage primary-si de-regulation pwm controller fo r pfc and led dimmable driving electrical characteristics v dd =15v and t a =25c unless otherwise specified. symbol parameter conditions min. typ. max. units over-current protection section ? v ocp v cs threshold voltage for ocp 0.60 0.67 0.74 v v lowocp v cs threshold voltage for low ocp 0.13 0.18 0.23 v t startup startup time 13 ms v lowocp-en vs threshold voltage to enable low ocp level 0.40 v v lowocp-dis vs threshold voltage to disable low ocp level 0.60 v over-temperature protection section t otp threshold temperature for otp (3) 140 150 160 o c t otp-hys restart junction temperature hysteresis 10 o c dimming section v dim-low maximum v dim at low dimming angle range 2.45 2.50 2.55 v v dim-high maximum v dim at high dimming angle range 3.43 3.50 3.57 v ds low v dim vs. v cs,offset slope at low dimming angle range 0.19 v/v ds high v dim vs. v cs,offset slope at high dimming angle range 0.58 v/v note: 3. if over-temperature protection is activated, the power system enters auto recovery mode and output is disabled. device operation above the maximum ju nction temperature is not guaranteed.
? 2011 fairchild semiconductor corporation www.fairchildsemi.com FL7730MY ? rev. 1.0.3 7 FL7730MY ? single-stage primary-si de-regulation pwm controller fo r pfc and led dimmable driving typical performance characteristics figure 5. v dd-on vs. temperature figure 6. v dd-off vs. temperature figure 7. i dd-op vs. temperature figure 8. v ovp vs. temperature figure 9. f max-cc vs. temperature figure 10. f min-cc vs. temperature
? 2011 fairchild semiconductor corporation www.fairchildsemi.com FL7730MY ? rev. 1.0.3 8 FL7730MY ? single-stage primary-si de-regulation pwm controller fo r pfc and led dimmable driving typical performance characteristics figure 11. v rv vs. temperature figure 12. v ccr vs. temperature figure 13. v ocp vs. temperature figure 14. v lowocp vs. temperature figure 15. ds low vs. temperature figure 16. ds high vs. temperature
? 2011 fairchild semiconductor corporation www.fairchildsemi.com FL7730MY ? rev. 1.0.3 9 FL7730MY ? single-stage primary-si de-regulation pwm controller fo r pfc and led dimmable driving functional description fl7730 is ac-dc dimmable pwm controller for led lighting applications. truecurrent tm technique and internal line compensation regulates accurate led current independent of inpu t voltage, output voltage, and magnetizing inductance variations. the triac dim function block provides smooth brightness dimming control compatible with a conventional triac dimmer. the linear frequency control in the oscillator reduces conduction loss and maintains dcm operation in a wide range of output voltages, which implements high power factor correction in a singl e-stage flyback topology. a variety of protections; such as short-led protection, open-led protection, over-t emperature protection, and cycle-by-cycle current limit ation; stabilize system operation and protect external components. startup powering at startup is slow due to the low feedback loop bandwidth in the pfc converter. to boost power during startup, an internal oscill ator counts 12ms to define startup mode. during start up mode, turn-on time is determined by current mode control with a 0.2v cs voltage limit and transconductance becomes 14 times larger, as shown in figure 17. after startup mode, turn- on time is controlled by voltage mode using the comi voltage and the error amplifier transconductance is reduced to 85mho. figure 17. startup sequence constant-current regulation the output current is esti mated using the peak drain current and inductor current discharge time because output current is same as the average of the diode current in steady state. t he peak value of the drain current is determined by the cs pin. the inductor discharge time (t dis ) is sensed by a t dis detector. using three sources of information (peak drain current, inductor discharging time, and operating switching period), a truecurrent? block calculates estimated output current. the output of the ca lculation is compared with an internal precise reference to generate an error voltage (v comi ), which determines turn-on time in voltage mode control. wi th fairchild?s innovative truecurrent? technique, c onstant current output can be precisely controlled. pfc and thd in a conventional boost converter, boundary conduction mode (bcm) is generally used to keep input current in phase with input voltage for power factor (pf) and total harmonic distortion (thd). however, in flyback / buck boost topology, constant turn-on time and constant frequency in discontinuous conduction mode (dcm) can implement high pf and low thd, as shown in figure 18. constant turn-on time is maintained by an internal error amplifier and a large external capacitor (typically >1f) at the comi pin. constant frequency and dcm operation are managed by linear frequency control. i in i in_avg gate constant frequency figure 18. input current and switching linear frequency control dcm should be guaranteed for high power factor in flyback topology. to maintain dcm in the wide range of output voltage, frequency is li nearly adjusted by output voltage in linear frequency c ontrol. output voltage is detected by auxiliary winding and resistive divider connected to the vs pin, as shown in figure 19. figure 19. linear frequency control
? 2011 fairchild semiconductor corporation www.fairchildsemi.com FL7730MY ? rev. 1.0.3 10 FL7730MY ? single-stage primary-si de-regulation pwm controller fo r pfc and led dimmable driving when output voltage decreases, secondary diode conduction time is increased and the linear frequency control lengthens switching period, which retains dcm operation in the wide output voltage range, as shown in figure 20. the frequency control lowers primary rms current for better power efficiency in full-load condition. l m nv o dis t l m vo 4 3 n dis t 3 4 l m vo 5 3 n di s t 3 5 t t 3 4 t 3 5 v o = v o.nom v o = 75% v o.nom v o = 60% v o.nom primary current secondary current figure 20. primary and secondary current bcm control the end of secondary diode conduction time can be over a switching period set by linear frequency control. in this case, fl7730 doesn?t allow ccm and operation mode changes from dcm to bcm. therefore, fl7730 originally eliminates sub-harmonic distortion in ccm. dimming control triac dimmable control is implemented by simple and noise-immune external passive components and an internal dimming function block. figure 21 shows dimming angle detection and the internal dimming control block. dimming angle is sensed by zener diode and zener diode voltage is divided by two resistors (r d1 and r d2 ) to fit the sensing range of the dim pin. the detected signal is f iltered by capacitor c d to provide dc voltage into the dim pin. the internal dimming control adds cs offset to the peak current value as the input of truecurrent? calculation block. when the dimming angle is small, lowered dim voltage increases cs offset , which makes calculated output current larger and reduces turn-on time to dim the led brightness. truecurrent calculation leb 1 cs 5 dim cs offset triac dim function cs offset dim vin v z r bias r d1 r d2 c d figure 21. dimming control schematic to disable the dimming functi on, a 1nf filter capacitor can be added at the dim pin. an internal current source (~7.5a) on the dim pin charges the filter capacitor up to 4v. fl7730 goes into ic test mode when dim voltage is over 6v; so the maximum dim voltage should be limited to less than 5v. short-led protection in a short-led condition, the switching mosfet and secondary diode are usually stressed by the high powering current. however, fl7730 changes the ocp level in a short-led condition. when v s is lower than 0.4v, the ocp level becomes down to 0.2v from 0.7v, as shown in figure 22, so that powering is limited and external components? current stress is relieved. figure 22. internal ocp block figure 23 shows operational waveforms in short-led condition. output voltage is quickly lowered to 0v after the led-short event. the reflected auxiliary voltage is also 0v, making v s less than 0.4v. the 0.2v ocp level limits primary-side current and v dd hiccups up and down in between uvlo hysteresis. figure 23. waveforms in short-led condition
? 2011 fairchild semiconductor corporation www.fairchildsemi.com FL7730MY ? rev. 1.0.3 11 FL7730MY ? single-stage primary-si de-regulation pwm controller fo r pfc and led dimmable driving open-led protection fl7730 protects external components, such as diodes and capacitors on the secondary side, in the open-led condition. during switch-off, the v dd capacitor is charged up to the auxiliary winding voltage, which is applied as the reflected output voltage. because the v dd voltage has output voltage information, the internal voltage comparator on the vdd pin can trigger output over-voltage protection (ovp), as shown in figure 24. when at least one led is ope n-circuited, output load impedance becomes very high and output capacitor is quickly charged up to v ovp x ns / na. then switching is shut down and v dd block goes into ?hiccup? mode until the open-led condition is removed, shown in figure 25. 4 internal bias vdd + - v ovp v dd good shutdown gate driver s r q v dd good figure 24. internal ovp block figure 25. waveforms in open-led condition under-voltage lockout (uvlo) the turn-on and turn-off thresholds are fixed internally at 16v and 7.5v, respectively. during startup, the v dd capacitor must be charged to 16v through the startup resistor to enable the fl7730. the v dd capacitor continues to supply v dd until power can be delivered from the auxiliary winding of the main transformer. v dd must not drop below 7.5v du ring this startup process. this uvlo hysteresis wi ndow ensures that the v dd capacitor is adequate to supply v dd during startup. over-temperature protection (otp) the built-in temperature-sensing circuit shuts down pwm output if the junction temperature exceeds 150c. while pwm output is shut down, the v dd voltage gradually drops to the uv lo voltage. some of the internal circuits are shut down and v dd gradually starts increasing again. when v dd reaches 16v, all the internal circuits start operating. if the junction temperature is still high er than 140c, the pwm controller shuts down immediately. frequency hopping emi reduction is accomplished by frequency hopping, which spreads the energy over a wider frequency range than the bandwidth measured by the emi test equipment. the internal frequency-hopping circuit changes the switching frequency 2.9khz.
? 2011 fairchild semiconductor corporation www.fairchildsemi.com FL7730MY ? rev. 1.0.3 8 FL7730MY ? single-stage primary-si de-regulation pwm controller fo r pfc and led dimmable driving physical dimensions figure 26. 8-lead , soic, jedec ms-012, .150" narrow body package drawings are provided as a service to customers consi dering fairchild components. drawings may change in any manner without notice. please note the revision and/or date on the drawi ng and contact a fairchild semiconductor representative to ver ify or obtain the most recent revision. package specifications do not expand the terms of fairchild?s worldwide terms and conditions, specifically the warranty therein, which covers fairchild products. always visit fairchild semiconductor?s online packagi ng area for the most recent package drawings: http://www.fairchildsemi.com/packaging/ 8 0 see detail a notes: unless otherwise specified a) this package conforms to jedec ms-012, variation aa, issue c, b) all dimensions are in millimeters. c) dimensions do not include mold flash or burrs. d) landpattern standard: soic127p600x175-8m. e) drawing filename: m08arev13 land pattern recommendation seating plane 0.10 c c gage plane x 45 detail a scale: 2:1 pin one indicator 4 8 1 c m b a 0.25 b 5 a 5.60 0.65 1.75 1.27 6.20 5.80 3.81 4.00 3.80 5.00 4.80 (0.33) 1.27 0.51 0.33 0.25 0.10 1.75 max 0.25 0.19 0.36 0.50 0.25 r0.10 r0.10 0.90 0.406 (1.04) option a - bevel edge option b - no bevel edge
? 2011 fairchild semiconductor corporation www.fairchildsemi.com FL7730MY ? rev. 1.0.3 13 FL7730MY ? single-stage primary-si de-regulation pwm controller fo r pfc and led dimmable driving

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